Marat Gershoig

Marat Gershoig is a Technical Manager at TSMC, where they have contributed over 20 years of experience in ASIC and FPGA high-speed digital design. Previously, Marat held various roles, including Senior FPGA/ASIC Designer at Edgewater Computer Systems and Prime ASIC Designer at Alvarion. They possess extensive expertise in Verilog and VHDL coding, synthesis tools, and advanced verification technologies, having worked with multiple vendors and various protocols. Marat earned a B.S. in Microelectronics from the Technion - Israel Institute of Technology and an M.S. in Electronics from the Moscow Institute of Electronics and Mathematics.