Mark Z. is a Principal Physical Design Engineer at TSMC, where they focus on physical implementation, design signoff verification, and methodology development for advanced processes. With a solid background in engineering management and technical staff roles at companies such as Cadence Design Systems and GLOBALFOUNDRIES, Mark has contributed to the development of various Process Design Kits (PDKs) and has extensive experience in optimizing design flows on cutting-edge technology nodes. Mark holds a Master’s degree in IC design from Shanghai Jiao Tong University and a Bachelor’s degree in Industrial Automation from Soochow University. Their career reflects a strong commitment to innovation and efficiency in the field of semiconductor design.
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