Ping-Han Tsai

Ping-Han Tsai is an advanced technology physical design engineer with extensive experience in SOC chip/block implementation, progressing from gate level netlist to GDS tape-out. Currently a Principal Engineer at 台灣積體電路製造股份有限公司, Ping-Han has over seven years of experience in multi-million gate count SOC design across various technology nodes, including 16, 12, 10, 7, and 5 nm. They possess a solid skill set in Cadence, Synopsys, and Mentor EDA tools, excelling in tasks such as P&R, CTS, timing closure, and physical verification. Ping-Han earned a Bachelor of Science in Photonics Engineering from National Chiao Tung University and a Master of Science in Electrical, Electronics, and Communications Engineering from National Taiwan University.