Ragadeep Bezawada possesses extensive experience in CPU design and physical design, highlighted by a tenure as Engineer IV at Qualcomm from September 2019 to July 2021, specializing in high-core CPU optimization, floorplan LEF sizing, and power analysis. Prior experience includes serving as a Technical Lead at Infotech Enterprises from August 2010 to July 2019, where expertise was developed in the flow from net list to GDS II and physical design using industry-standard tools. Additionally, Ragadeep completed an internship at Synopsys in early 2010 and held a role as Senior Physical Design Engineer at Blaize in mid-2019, currently advancing the field as a Principal Engineer at TSMC since July 2021. Educational qualifications include a B.Tech in Electronics and Communication Engineering from Gudlavalleru Engineering College and an M.Tech in VLSI & ES from the International Institute of Information Technology.
This person is not in the org chart
This person is not in any teams
This person is not in any offices