Satyabrata Dash

Satyabrata Dash is a Principal Engineer in the Layout Design Engineering Division at TSMC, where they have been involved in designing and validating standard cell layouts for advanced technology nodes since 2022. They previously held the same position from 2019 to 2022 at TSMC, contributing to layout methodology development and creating automated programs to enhance productivity. Prior to TSMC, Satyabrata served as a contractual Assistant Professor at the National Institute of Technology Mizoram. They earned a PhD in VLSI CAD from the Indian Institute of Technology, Guwahati, and have a Bachelor of Technology in Electrical, Electronics and Communications Engineering.