Sumana Mitra

Sumana Mitra is an accomplished engineer with extensive experience in IC layout design, currently serving as a Principal Engineer at TSMC since October 2013. Sumana's strong expertise includes high-speed custom SRAM memory compiler layout utilizing advanced FinFET processes ranging from 20nm to 3nm with dual pattern technology, employing tools such as Cadence Virtuoso 18 VXL. Prior to TSMC, Sumana worked as an IC layout designer at IC Enable and ARM, where contributions included projects on the 14nm FinFET process and 20nm custom single port memory compilers. Sumana began the career with an internship at Hindustan Motors India Ltd. and holds a B.Tech degree in Electrical Engineering from Haldia Institute of Technology, completed in 2002.