Tung Le is a Yield Engineer at TSMC since May 2021, focusing on defect reduction and data analysis to enhance semiconductor production processes. Prior to this role, Tung served as a Process Engineer at Intel Corporation from March 2019 to May 2021, where responsibilities included troubleshooting semiconductor processes and applying statistical methodologies. Tung has also worked as a Test Engineer and Certified Test Engineer at TRAX International Corporation, engaging in testing military systems, and served as an Undergraduate Teaching Assistant at Ira A. Fulton Schools of Engineering at Arizona State University. Educational qualifications include a Bachelor of Engineering in Chemical Engineering and a Bachelor of Science in Botany/Biology from Arizona State University.
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