Arathi J.

Arathi J. is a Technical Lead I in VLSI at UST, where they contribute to advanced verification processes. With experience spanning multiple roles in design verification at companies like Invecas Technologies and MACOM, Arathi has specialized in SOC-level verification for various protocols. They completed a Master’s degree in VLSI and Embedded Systems from SGGS College and hold a Bachelor of Engineering in Electronics Engineering from D.K.T.E Institute. Arathi has also undergone training in System Verilog at Mentor Graphics, enhancing their expertise in the field.