Jagadeesan M is a dedicated and results-oriented Senior Validation Engineer at UST, specializing in post silicon validation and validation testing. Previously, they held a position as a Junior Engineer at Rising Star Mobiles India Private Limited from 2017 to 2020 and worked at Avalon Technologies Pvt Ltd in 2016-2017. Jagadeesan holds a Bachelor of Engineering in Electronics and Communication from IFET College of Engineering, which they completed in 2016. They have substantial experience with various validation processes, including UEFI BIOS flashing and functional testing on both 14 nm and 10 nm processors.
Location
Bengaluru, India
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