Rohit Bobade

Rohit Bobade is a Lead RTL Design Engineer with extensive experience in RTL design using VHDL and Verilog. They have worked for UST since 2022, after serving as a Sr RTL Design Engineer at the same company from 2018 to 2022, focusing on front-end activities for multiple SoCs with Intel and NoC design for Qualcomm. Prior to UST, Rohit was a VLSI Engineer at Wipro Technologies and an RTL Design Engineer at Kuberre Systems, where they managed high-speed data processing and integration for various protocols. Rohit earned a degree in VLSI and Embedded Systems from the College of Engineering Pune and a Post Graduate Diploma in VLSI from CDAC.