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Vishwanath Poluru

UST

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Vishwanath Poluru

Senior Pre and Post Silicon Validation Engineer

Vishwanath Poluru is a BIOS/EC Firmware Validation Engineer actively seeking new opportunities after serving their notice period. With over 2 years of experience in IT, they have a strong background in analyzing and validating hardware, focusing on Firmware/Embedded validation, BIOS Validation, and Pre & Post Silicon validation. Previously, Vishwanath served as a VLSI design and verification trainee at Maven Silicon, and held various roles including Associate Silicon Validation Engineer and Senior Pre and Post Silicon Validation Engineer at UST. They hold a Bachelor of Technology in Electronics and Communications Engineering with distinction from Rajeev Gandhi Memorial College of Engineering and Technology.

Location

Bangalore Rural, India

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