Yugesh D

Yugesh D is a seasoned Lead Verification Engineer with expertise in System Verilog, UVM, and Linux. With experience at companies like Intel Corporation and Qualcomm, they are currently serving as a Senior Verification Engineer while also holding a position as Lead Engineer DV at UST. Yugesh holds a Bachelor’s Degree in Electronics and Communications Engineering and a Master’s degree in Embedded Systems, both with First Class distinction.