佳禛 缑

佳禛 缑 has extensive work experience in the field of verification engineering. They started their career as a Design Verification Engineer at 信源通科技(西安)有限公司 in 2009 and worked there until 2011. In this role, they were responsible for RTL and gate-level verification code for Intel-based chip validation, as well as software testing and bug analysis on the testing platform.

From 2011 to 2014, 佳禛 缑 worked at 西安华洲半导体有限公司 as a Project Verification Manager. Their responsibilities included starting the Verification Organization and leading the verification process for SD/eMMC/SDIO modules. They also performed RTL and gate-level verification for the company's projects.

From 2015 to 2020, 佳禛 缑 worked as a Staff Verification Engineer at 英特尔, where they contributed to the verification of SD/eMMC/SDIO modules, RTL, and gate-level verification code. They also performed software testing, bug tracking, and resolution.

In 2020, 佳禛 缑 joined 浪潮 as a Verification Manager. They continued to lead the verification process and ensure the quality of the company's projects.

In 2021, 佳禛 缑 joined 昂特尔半导体 as a Verification Manager, where they are currently serving in that role.

Overall, 佳禛 缑's work experience demonstrates their expertise in verification engineering and their ability to lead verification processes and ensure project quality.

佳禛 缑 completed a Bachelor's degree in Microelectronics at Xidian University from 2004 to 2008. 佳禛 then pursued a Master's degree in Microelectronics at the same university from 2008 to 2011.