Marc Radzikowski possesses extensive experience in electrical engineering, currently serving as Lead Engineer at Vertiv since March 2006. In this role, Marc is the lead designer and a patent holder for next-generation products focused on analog signal acquisition, processing, and measurement. Notable achievements include the successful migration of designs from Spartan-6 to Spartan-7 devices, involving complex revisions in VHDL code and the implementation of BGA packages on a 6-layer printed wiring board. Prior to Vertiv, Marc worked as a Process Engineer at Profab Electronics, where responsibilities included preparing customer designs for electronic assembly and conducting electronic design evaluations and circuit analysis. Marc holds a Bachelor of Science in Electrical Engineering from Stony Brook University, attained between 1998 and 2003.
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