Angelo B.

Angelo B. is an experienced developer specializing in low latency systems at Virtu Financial since February 2019. Prior to this, Angelo B. worked at Xilinx as a DSV Engineer in the Software and IP Group, focusing on system-level design and test design developments for Xilinx implementation tools. Previous roles include a Digital Hardware Designer at Skytechnology SRL, where the design and development of signal processing systems for Software Defined Radios were key responsibilities, and a short-term scientific mission at the European Space Agency, studying radiation effects on DRAMs. Angelo B. also completed an internship at the European Space Agency, where FPGA-based DRAM testing was a primary focus. Earlier experience includes freelancing at Dedilab and a robust educational background in Electronics Engineering, culminating in a Master's degree from the University of Rome Tor Vergata.