Tomasz Tarkiewicz

Tomasz Tarkiewicz is a Technical Manager at Vtool Poland, specializing in IP, sub-system, and SoC verification. They have extensive experience in ASIC/FPGA design and verification, including the use of System Verilog, UVM methodology, and various verification processes. Tomasz previously held positions as Principal Verification Engineer at Cadence Design Systems and FPGA Verification Senior Engineer and Lead Engineer at Nokia, contributing to 5G FPGA projects. They obtained a Master's degree in Electronics and Telecommunications from Politechnika Śląska w Gliwicach in 2008.