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VVDN Technologies
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RTL Design Engineering
32 people · 0 jobs
This department focuses on the design and development of RTL (Register Transfer Level) specifications and implementations for FPGA and ASIC technologies.
Abhijith S
Sr Engineer (RTL)
Aiswarya R Nair
Senior RTL Design Engineer
AKSHAYA PRAKASH K
Sr. RTL Engineer
Anagha A
RTL Design Engineer
ANJALI SUKUMARAN M
Rtl design engineer
Anju K.
ARYA KR
RTL/FPGA DESIGN ENGINEER
Bala Nagavardhan Kandukuri
RTL design Engineer
Chandana Elizabeth Peter
Engineer - RTL Design
Chriswin George
Dr. Jithin Kumar M. V.
Senior RTL Engineer
Jismy Jelson
K.V.S Vamsi krishna
Senior RTL Design Engineer(FPGA)
Mohammad Afnan
RTL DESIGN ENGINEER
Muthu Malar M
Nandu Vijayan
Nayana Thara
Nithya Sri Mahendran
Rtl Design Engineer
Omkar Taware
RTL Design and FPGA Engineer
Prasanth C
Sr Manager (rtl Design)
Prigish George Abraham
Senior FPGA RTL Design Engineer
Purushotham Gandeti
RTL Engineer
Rakshitha M
RTL design engineer
Sarath K S
Tech Lead Rtl/fpga Design
Sarath M
Selvakumar A
Senior FPGA/RTL Design Engineer
Shahid K K
Sr. FPGA/RTL Design Engineer
Shincy M
Sivanantham Palaniappan
FPGA RTL design Engineer
Sona Prakash
RTL/FPGA Design Engineer
Sourabh Kole
RTL And FPGA Design Engineer
Vidhya N
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