Lalith kumar

Lalith Kumar is a Senior Verification Engineer at Wipro, where they apply their strong understanding of ASIC and FPGA flows, as well as digital logic design and verification using Verilog and System Verilog. With hands-on experience in writing synthesis RTL and building UVM, they have also utilized industry-standard EDA tools such as Xilinx ISE, Questa SIM, and Aldec Viera Pro. Previously, Lalith held verification engineer positions at Motax Solutions, Confiable Amico, and Insemi Technology Services, and earned a Bachelor of Technology in Electronics and Instrumentation from Sree Vidyanikethan Engineering College, followed by a PG diploma in VLSI design from Maven Silicon Pvt Limited.