Maninder Singh is a seasoned engineer with extensive experience in the field of electronics and communication, holding a B.Tech from Punjab Technical University and an MS in Electrical Engineering from California State University-Northridge. Currently serving as a Sr. Engineer at Wipro since January 2016, Maninder specializes in physical aware synthesis and static timing analysis for high-speed Serdes IP using advanced technologies. Prior roles include Design Engineer at Freescale Semiconductor, where contributions involved RTL design and performance analysis, as well as ASIC Flow Research Assistant at Cal State Northridge and ASIC Verification Intern at PerfectVIPs, where responsibilities included assisting with hardware and software usage and verifying SATA device controllers, respectively. Early career experience also includes training at Synopsys Inc. and support roles in academia.
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