Mohammed Rabil is an ASIC Design Verification Engineer with expertise in PCIe, NVMe, AXI, Systemverilog, UVM, Verilog, and Synopsys_VCS. They served as a Senior Engineer in ASIC Verification at Altran from 2017 to 2019, followed by a role as Lead Engineer at Cerium Systems from 2019 to 2021. Currently, they work as a Technical Lead at Capgemini Engineering after a previous role at Wipro from 2024. Mohammed holds a Bachelor of Engineering in Electrical, Electronics, and Communications Engineering from Anna University and a Diploma in Electronics and Communications Engineering from Aalim Muhammed Salegh Polytechnic College.
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