Pavan M

Pavan M is a Hardware Design Verification Engineer with experience in functional verification at both IP and SOC levels. Pavan worked at L&T Technology Services Limited and AppEx Semiconductors as a Design Verification Engineer before becoming a Senior Design Verification Engineer at Wipro in 2021. Pavan holds a Bachelor of Engineering in Electronics and Communications Engineering from Visvesvaraya Technological University, graduating with first class honors. Pavan possesses skills in Verilog, System Verilog, UVM, and various digital concepts.