vicky chavan

Vicky Chavan is a Senior Design Verification Engineer at Wipro Limited, where they are currently validating Gate Level Netlist of an SoC-based project using DualSim GLS simulation. With extensive experience in debugging and a strong skill set in Verilog, SystemVerilog, and UVM, Vicky has developed and implemented verification plans for multiple subsystem IPs, including PCIe protocols. They hold a Bachelor of Technology from Veermata Jijabai Technological Institute (VJTI), which they completed in 2017.