Peter Grossmann

Peter Grossmann has a work experience of over 20 years in ASIC and FPGA design, verification, and production-test bring-up. Peter worked as a Principal Engineer at Zero ASIC from May 2022, where they were responsible for developing automation techniques for end-to-end flow of FPGA circuits. Prior to this, they worked at Intrinsix Corp. as a Solutions Architect and a Principal Consulting Engineer from 2019 to 2022, where they co-led a multi-organization team performing government-sponsored research and presented work to research program sponsors. Peter was a Technical Lead at MIT Lincoln Laboratory from 2013 to 2019, where they led a team of six engineers developing field programmable imaging arrays. Peter was also a Lincoln Scholar and an Associate Staff at MIT Lincoln Laboratory from 2007 to 2013, where they designed and verified integrated circuits using Cadence and Mentor EDA tools and fabricated subthreshold FPGA test chips. Peter started their career in 2001 as an ASIC Design Engineer at Zilog, where they participated in design, verification, and production-test bring-up for high-performance 8-bit microcontrollers.

Peter Grossmann received a Bachelor of Science degree in Engineering from Harvey Mudd College. Peter then pursued a Master of Science degree in Electrical Engineering at the University of Washington from 2005 to 2006. From 2009 to 2013, they obtained a Doctor of Philosophy degree in Computer Engineering from Northeastern University.