Hamid Yadegar Amin

Hamid Yadegar Amin has extensive experience as an Analog RFIC Design Engineer, with roles at Acconeer AB (from 2023), Sivers Semiconductors AB (formerly Sivers IMA) (from 2021 to 2023), NXP Semiconductors (from 2020 to 2021), and Catena Group (from 2019 to 2020). Prior to these positions, Hamid worked as a Research Assistant at Chalmers University of Technology (from June 2019 to September 2019), University of Oulu (from August 2016 to June 2018), and Istanbul Technical University (from January 2015 to January 2016). At Chalmers University of Technology, Hamid contributed to the design of a low power LO phase shifting phased array receiver for sub-30 GHz 5G (FR2) bands.

Hamid Yadegar Amin completed their Bachelor's degree in Electrical and Electronics Engineering from Urmia University between 2007 and 2011. Hamid then pursued a Master's degree in Electrical, Electronics, and Communications Engineering from Istanbul Technical University from 2012 to 2014. Recently, between 2018 and 2020, they completed another Master's degree in Embedded Electronics from Lund University.