Meghana Dachepally

Meghana Dachepally is a Senior Verification Engineer at ACL Digital since May 2021. Prior to this role, Meghana worked as a GFX DV Engineer at AMD from May 2021 to February 2023 and as a Design Verification Engineer I at RiseTime Semiconductors from December 2019 to May 2021. Additional experience includes positions as an Application DV Engineer at Cadence Design Systems, an Associate DV Engineer at BlackPepper Technologies Pvt Ltd, and an RTL Design Verification Trainee at SumedhaIT. Meghana began professional experience with an internship at Bharat Sanchar Nigam Limited. Educational qualifications include a Master of Technology (MTech) in VLSI-SD from CVR College of Engineering and a Bachelor of Technology (BTech) in Electronics and Communication Engineering from JNTUH College of Engineering Hyderabad.