Amit M.

Amit M. is an experienced professional in the field of design for testability (DFT) and related areas, currently serving as a DFT RTL Architect/Sr. Manager at AMD since February 2023, focusing on DFT architecture, RTL design, and ATPG for CPU cores. Prior to this role, Amit held positions at Cerebras Systems as DFX for Wafer Scale Engines, and at Esperanto Technologies, Inc. as DFX Engineering Manager, where responsibilities included leading and managing the DFX team. Additional experience includes serving as a DFT Architect at Cavium Inc, a DFT Lead/Architect at Synopsys, a Sr. Product Engineer at Xilinx, a Member of Technical Staff, DFT at Sun Microsystems, and as a DFT Design Engineer at Micron Technology. Amit holds a Master's degree in Electrical Engineering from Northern Illinois University and a Bachelor's degree in Electronics Engineering from Walchand Institute of Technology, Solapur.