Annesa Rahman

Annesa Rahman is a Senior Silicon Design Engineer at AMD with extensive experience in systems engineering, emulation, and debug. Since July 2020, Annesa has been responsible for planning, test plan development, and both pre-silicon and post-silicon testing for chip IP across various customer programs. Serving as the RAS product owner and domain lead, Annesa has developed cross-IP test plans, managed program risks, and executed pre- and post-silicon tests. Annesa's prior experience includes a Hardware Design Engineer Internship at AMD, where skills in memory tuning and diagnostics were honed, and a Machine Learning Research Assistant position at Ryerson University, contributing to the development of a seizure prediction device. Currently pursuing a Master of Engineering in Computer Engineering at the University of Toronto, Annesa holds a Bachelor's Degree in Biomedical Engineering from Ryerson University.