Deepak TS

Deepak TS is currently a Verification Engineer at AMD, having previously held roles as a Senior Design Verification Engineer and a Silicon Design Engineer. They have extensive experience in hardware engineering, with significant projects including the design of a 5-stage pipelined processor for RISC V ISA using SystemVerilog and analog schematic/layout design on Cadence. Deepak earned a Master's degree in Electrical and Computer Engineering from Boston University and a Bachelor's degree in Electronics and Instrumentation Engineering from Amrita Vishwa Vidyapeetham. They also served as a Teaching Assistant at Boston University and worked as a Visiting Researcher.