Grace Elias

Grace Elias is an experienced engineer specializing in SERDES IP design, with a career spanning over two decades in the semiconductor industry. Currently serving as an MTS Design Engineer at AMD since 2014, Grace previously held the position of Senior ASIC Engineer at the same company and has contributed significantly to the development of Analog and Mixed Signal IPs for AMD's latest GPU and Fusion products. Grace's foundational experience includes roles as an ASIC Test Engineer and an ASIC Design Engineer, along with an earlier position as an FPGA Design Engineer. Academic qualifications include a Master's and Bachelor's degree in Electrical Engineering from the University of Ottawa.