Haresh Patel is a Senior Member of Technical Staff at AMD, having previously served as a Senior Hardware Validation Engineer at Intel Corporation from 2017 to 2023. With a background in Electronics and Communication, Haresh holds a B.E. from SVIT and an MS from Northwestern Polytechnic University. Throughout their career, Haresh has demonstrated expertise in hardware validation, technical debugging, and innovation in validation lab debug tools, earning recognition for leading cost-saving transformations and enhancing validation processes. Prior internship experiences include positions at JC Technolinks and Bharat Sanchar Nigam Limited in India.
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