Jigneshkumar Patel

Jigneshkumar Patel is an experienced ASIC Design Verification Leader with over 19 years in the semiconductor industry, currently serving as a Senior Member of Technical Staff at AMD since 2025. They have held significant roles in verification, including as a Senior Verification Project Lead at Intel Corporation from 2016 to 2025, and have demonstrated expertise in SOC design integration and validation, as well as IP and SoC-level validation. Jigneshkumar has been recognized for their innovative solutions, including implementing tools that significantly reduced file sizes and debug times. Additionally, they contribute to the industry as the Chairperson of the Silicon Design Verification Group for IEEE's Sacramento Section. Jigneshkumar holds a B.E. in Electronics & Communication from Sardar Patel University and a diploma in the same field from Government Polytechnic, Gandhinagar.