Mallesh Balla is a Sr. Silicon Design Engineer at AMD, where they focus on ATPG simulations. Previously, Mallesh worked as a DFT Engineer at Texas Instruments and Samsung Semiconductor India, specializing in ATPG simulations and scan insertion. They began their career as an ATE Engineer and later transitioned to a DFT Engineer role at Tessolve Semiconductor Pvt. Ltd. Mallesh holds a Bachelor of Engineering in Electronics and Communication Engineering from Jawaharlal Nehru Technological University, Kakinada.
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