Parth Bir is a Senior PnP silicon architect at AMD, where they have been contributing since 2025. Previously, they worked as a Senior Performance Verification Engineer in GPU_HW at Qualcomm from 2021 to 2025 and held various engineering roles, including a High Performance Computing Engineer at Argonne National Laboratory in 2020. Parth also gained experience as an R&D Engineer at Oneirix Labs and completed several internships, including at Cadence Design Systems and the Indian Institute of Technology, Madras. They have been a reviewer for the Journal of Supercomputing at Springer Nature since 2019 and earned a Bachelor of Technology in Electronics and Communications Engineering from APJ Abdul Kalam Technological University in 2020.
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