Peter M

Peter M is an AI and HPC architecture leader currently pursuing a Master of Science in Electrical and Computer Engineering at the University of California, Berkeley. They previously served as Chief System Architect at AMD, where they led design efforts to maximize I/O throughput on the EPYC CPU platform. Prior to that, Peter held the position of Chief SoC Architect at Hewlett Packard Enterprise, focusing on GPU and AI accelerator architecture for cloud computing and data center platforms. Their earlier experience includes designing high-bandwidth I/O solutions and optimizing communication architectures as a Senior Systems Engineer and System Engineer.