Riyas NR

Riyas NR is a Principal Design Engineer at AMD, specializing in FPGA, UCIe, low latency, and photonics PHY. With extensive experience in high-speed data path design, Riyas has worked on SmartNIC product development and contributed to the architecture of software-defined ANLT solutions. Their background includes significant roles at Xilinx, where they engaged in 28nm-16nm designs, and ARM, where they architected multi-processor systems. Holding a Master’s degree in System on Chip from the University of Southampton, Riyas is also credited with more than seven patents related to latency measurement techniques and low latency data transfer.