Vu Pham

Vu Pham is a Senior Design Engineering Manager at AMD, bringing over 24 years of experience in building and managing high-impact teams specializing in Serdes PHY design for PCIe, Ethernet, and other protocols. Previously, Vu held positions at Xilinx and served as a Staff Design Engineer, along with various roles at companies like AppliedMicro, ST-Ericsson, and Arrive Technologies, focusing on design verification and firmware engineering. Vu possesses a strong background in verification methodologies, including AVM, OVM, and UVM, and is skilled in languages such as Verilog, SystemVerilog, and Perl. Vu earned an MBA in Management from Ho Chi Minh University of Technology and obtained multiple certifications related to SystemVerilog and project management.