Keshav Kinkar Sonbhadra

Keshav Kinkar Sonbhadra is a seasoned engineering professional specializing in design verification with extensive experience in the semiconductor industry. Currently serving as a Senior Design Verification Engineer at Aeva since July 2021, Keshav focuses on advanced LIDAR technologies, employing UVM, System Verilog, and Object Oriented Concepts for ASIC and FPGA verification. Prior roles include an ASIC Verification Engineer at Juniper Networks, where Keshav contributed to UVM and SystemC based verification for ASICs, and a SoC Verification Engineer at Intel Corporation, involved in verification and validation of Intel Xeon 10nm SoCs. Keshav's academic qualifications include a Master of Science in Electrical Engineering from the University of Southern California and a Bachelor of Engineering in Electronics and Instrumentation from Birla Institute of Technology and Science, Pilani.