Francisco Javier Badenas

Francisco Javier Badenas has extensive work experience in the field of ASIC Digital Physical Design. Francisco Javier started their career at UTN Buenos Aires, where they worked as an Undergraduate Researcher in the Nanoelectronics Lab. During this time, they were responsible for tasks such as HDL integration, physical design, fabrication, and testing of digital integrated circuits. Francisco Javier also served as an Assistant Teacher, where they taught theoretical topics and supervised FPGA development kits.

In 2020, Francisco joined Allegro MicroSystems as a Digital Physical Design Engineer. Here, they were involved in various aspects of ASIC design, including synthesis, logic equivalence checks, place and route, DFT/ATPG, static timing analysis, and power analysis. Francisco Javier also developed software and scripts using TCl, Python, and Bash for internal use. In addition, Francisco automated design flows using Continuous Integration.

Due to their expertise and contributions, Francisco was promoted to the role of Digital Physical Designer, Team Lead at Allegro MicroSystems. As a Team Leader for Backend/P&R in Argentina, they led a team in executing various design tasks and ensuring the successful completion of projects.

Overall, Francisco Javier Badenas has a strong technical background in ASIC Digital Physical Design and has gained valuable experience in both research and industry settings.

Francisco Javier Badenas completed their education with a degree in Electronics Engineering from Universidad Tecnológica Nacional in 2020. Francisco Javier also spent a year as an interchange student at Technische Universität Dresden, studying Electronic Engineering from 2018 to 2019. Prior to that, they obtained a certification as an Electronics Technician from Instituto Tecnológico San Bonifacio, where they studied from 2006 to 2010. In addition to their formal education, Badenas has obtained several certifications in various areas of electronics and engineering from Cadence Design Systems, including low-power specification format, implementation systems, static timing analysis, and power grid analysis.