Tej Kola

Tej Kola is a dedicated Design Verification (DV) Engineer with a Bachelor of Technology in Electrical Engineering from the National Institute of Technology Rourkela, class of 2021. Currently employed as a VLSI Engineer at Wipro Limited and a Senior Design Verification Engineer at Altera, Tej has cultivated extensive experience in debugging and validating digital designs, particularly using Verilog, SystemVerilog, and UVM methodologies. Tej has previously worked at Intel Corporation, contributing to significant projects such as USB and CNV Specman. Additionally, Tej has engaged in various roles, including as a summer trainee at Odisha Power Transmission Corporation Limited and as a coordinator for events at Innovision and Nitrustav.