Dingxin Jin

Dingxin Jin is a highly skilled Staff ASIC Design Engineer at Ambarella Inc, with experience in high-speed memory controller design for the latest LPDDR generations and the development of a deformable interpolation block for data resampling, accumulating expertise since February 2020. Prior roles include Senior ASIC Design Engineer and ASIC Design Engineer, along with a brief internship as an ASIC Design Engineer Intern where focus was on system-level debug interface verification. Prior to joining Ambarella, Dingxin Jin conducted research in secure hardware as a Graduate Student Researcher at the Georgia Institute of Technology under Prof. Abhijit Chatterjee. Educational background includes a Bachelor's degree in Electrical and Electronics Engineering from Southeast University and further studies at the Georgia Institute of Technology.