Naynesh Shah

Naynesh Shah is a Principal Engineer at Ampere, specializing in emulation since December 2021. Previously, Naynesh held various engineering roles at Cadence Design Systems from November 2014 to November 2021, where responsibilities included resolving product issues, debugging failures, and collaborating with R&D teams. At Qualcomm, Naynesh worked as a Verification Engineer on UVM-based internal bus protocol verification from September 2013 to October 2014. Additional experience includes roles at PerfectVIPs focused on PCIe Gen 3.0 PHY layer verification, a Student Assistant position at California State University, Northridge, and early career roles in embedded systems design at Mtech Innovations Ltd and Nital Computers. Naynesh holds an M.S. in Electrical Engineering from California State University, Northridge, a B.E. in Electronics and Telecommunication from Savitribai Phule Pune University, and a Diploma in Industrial Electronics from SVCP.