Phu Huynh

Phu Huynh is an accomplished engineer with extensive experience in the electronics and computer engineering sectors. Currently serving as the CPU Post Silicon Validation Lead at Ampere since February 2022, Phu previously held the position of Verification Architect at Cadence Design Systems for over 18 years. Notable early career roles include serving as CTO and Co-Founder at SanBar Networks, Engineering Director at Cadence Design Systems/Tality, and Sr Engineer at Cisco Systems. Furthermore, Phu contributed to Delco/Hughes Electronics as a Fault-tolerant Computer System Architect and began a career in ASIC/Computer Design at Delco Electronics. Educational qualifications include a Master of Science in Electrical & Computer Engineering and a Bachelor of Science in Electrical and Computer Engineering, both attained from UC Santa Barbara.