Yoham Parelkar

Yoham Parelkar is an accomplished engineer with extensive experience in package and systems engineering. Currently, serving as an L-8 Principal Package & Systems Engineer at Ampere since February 2019, Yoham collaborates with chip and hardware designers to deliver packaging solutions ensuring robust signal and power integrity performance. Proficient in simulating high-speed DDR I/O and developing PCB layout guidelines, Yoham utilizes advanced tools such as HyperLynx SI/PI, ANSYS Nexxim, and Keysight ADS. Previous roles include engineering internships at Micro Systems Engineering, Inc., where Yoham worked on battery longevity simulations and wireless communication hardware, and serving as an Assistant System Engineer at SIL Technologies. Yoham holds a Master's degree in Electrical and Electronics Engineering from California State University, Fullerton, and a Bachelor of Engineering from Vidyalankar Institute Of Technology.