玥崔 started their work experience in 2008 at Huawei as an FPGA development engineer. In this role, they were responsible for netstream module level document/RTL design/verification/synthesis. 玥 worked there until 2011. In 2012, they joined Analogix Semiconductor Inc. as a Project Leader of ASIC design.
From 2004 to 2008, 玥 崔 attended Tianjin University, where they earned a Bachelor's degree in Microelectronics.
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