Murat Becer

Murat Becer is a seasoned professional in the field of electrical engineering with extensive experience in research and development. Currently serving as VP R&D at Ansys since July 2015, Murat previously held the position of Sr Director R&D at the same company after founding Gear Design Solutions in July 2012, which specialized in Big Data for Chip Design and was acquired by Ansys in 2015. Prior roles include Senior Staff R&D at Synopsys, focusing on PrimeTime R&D, and Senior Engineer at CLK Design Automation, where core delay calculation and signal integrity engines were developed. Murat's career commenced at Motorola/Freescale Semiconductor as a Senior Staff Engineer, contributing to tools and methodologies for signal integrity closure. Educational credentials include a Ph.D. in Electrical Engineering from the University of Illinois Urbana-Champaign and a BS in Electrical Engineering from Boğaziçi University.