Hemanth kumar Kotlapati

Hemanth Kumar Kotlapati has been working in the semiconductor industry since 2018. Hemanth kumar began their career as an ASIC Design Engineer (DFT) at Open-Silicon, Inc., where they were responsible for scan insertion, Mbist insertion, Rom bist insertion and Atpg analysis, IP testing such as PLL, USB. Hemanth kumar also did verification for mbist, stuckat, atspeed, bscan, as well as post silicon pattern generation and post silicon debug. In 2019, they moved to Mirafra Technologies, where they worked as a DFT Engineer 1, handling ATPG-SAF activities for 5nm Technology Design. Hemanth kumar also debugged Violations like T,K,F,P94 and improved Core/Block SAF Coverage to 99.5%. In 2021, they began working as a Senior Design Engineer at Apex Semiconductor.

Hemanth Kumar Kotlapati completed a Bachelor of Technology in Electrical and Electronics Engineering from Audisankara College of Engineering & Technology, Gudur between 2010 and 2014. Hemanth kumar then went on to pursue a Master of Technology in VLSI System from the National Institute of Technology, Tiruchirappalli between 2016 and 2018.