Chengchuan Qu

Chengchuan Qu is a DV Engineer at Apple since June 2019, following nearly a decade of experience at AMD from May 2010 to June 2019, where roles included MTS ASIC Design Engineer for SOC Integration and DFTIP, and Sr. ASIC Design/Layout Engineer. At AMD, notable achievements included optimizing DFT design, leading DFT for new IP, and receiving the Next 5% Award for contributions to DV infrastructure. Chengchuan's expertise encompasses JTAG/MBIST/SCAN deployment in RTL, coordination with global teams, and development of scalable DFT IP for various SOC designs. The educational background includes a Bachelor of Applied Science in Electrical and Electronics Engineering from the University of Toronto, completed in 2010, alongside earlier studies at Glenforest Secondary School.