Jean-Christophe Pellion

Jean-christophe Pellion has extensive work experience in the field of digital design and verification. Jean-christophe is currently working as a Senior DV Engineer at Arteris IP since January 2021. Prior to this, they worked at Nokia from August 2017 to January 2021, where they held the position of Soc / IP Specialist - (Design, Verification & Architect 5G NR L1). Before joining Nokia, they worked at EASii IC as an FPGA & ASIC Digital Frontend Engineer from October 2007 to August 2017. Jean-christophe also worked as a subcontractor at CEA from January 2016 to April 2017, at CNRS from October 2012 to October 2015, and at Bull from 2011 to 2012. From October 2007 to November 2009, they worked as an ASIC Digital Designer subcontractor at ST-Ericsson, where they were involved in projects related to ASIC Baseband 8530 and ASIC Baseband PC SALLY/ SALLY, with responsibilities including integration of the Display Subsystem and design and integration of the System Controller.

Jean-christophe Pellion attended Polytech'Nice-Sophia from 2001 to 2006, where they pursued a degree in MicroElectronics. Following that, in 2006, they briefly studied at the Université Côte d'Azur, specializing in Embedded Systems and obtaining a Master of Information and Communication Sciences and Technologies degree.