JL

Jongyup Lim

SoC Power Model Engineer

Jongyup Lim is an accomplished researcher and engineer specializing in electrical and computer engineering. With experience as an Academic Guest at ETH Zürich, Jongyup contributed to the design of a low-power wireless neural recording IC. As a Graduate Research Assistant at the University of Michigan, significant projects included a miniaturized wireless neural recording IC, an energy-efficient all-analog ResNet accelerator, and a gate-leakage-based timer. Internships at Apple involved developing core display technologies and enhancing test coverages for display systems, while an internship at Dongbu HiTek focused on display design. Jongyup holds a Bachelor's degree in Electrical and Electronics Engineering from Seoul National University, graduating summa cum laude, as well as a Master's and a PhD from the University of Michigan.

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Cupertino, United States

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