Vishal Kedia

Vishal Kedia is a seasoned engineer specializing in semiconductor design and physical design methodology with over 19 years of experience across various prominent companies. Currently serving as a SoC Physical Design Engineer at Apple since October 2018, Vishal focuses on timing path analysis, infrastructure implementation, and collaboration with design teams for timing optimization. Previously, as a Sr Staff ASIC Engineer at Juniper Networks, Vishal developed fullchip methodology and enhanced physical design flows. At Intel Corporation, significant contributions were made as a Component Design Engineer, leading timing closure for high-frequency designs. Early career experiences include impactful roles at Synopsys, where Vishal influenced the development of IC Compiler and PrimeTime tools. Vishal holds an MS in Electrical Engineering from Stanford University and a B.Tech in Electrical Engineering from the Indian Institute of Technology, Delhi.